Press Room - Latest Press Releases

The MathWorks today introduced Simulink® HDL Coder, which automatically generates synthesizable hardware description language (HDL) code from models created in the company's widely-used Simulink and Stateflow ® software. The product produces target-independent Verilog and VHDL code and test benches for implementing and verifying application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs).  By providing a path directly from system models, Simulink HDL Coder accelerates the design, implementation, and verification of hardware. 

"For years, electronics designers have eagerly anticipated the arrival of a method to automatically synthesize software code to an ASIC or FPGA from system models," said Handel Jones, CEO of International Business Strategies, Inc. "With Simulink HDL Coder, this game-changing solution now brings the long-discussed promises of electronic system-level design closer to reality. With a direct path from a Simulink executable specification to HDL, design teams will dramatically reduce the time, cost, and quality pressures they face in an increasingly competitive market."

"For more than a decade, engineers have been using Model-Based Design to achieve reductions in development time of 50% or greater for system, board, and IC designs," said Ken Karnofsky, director of marketing, signal processing and communications, The MathWorks. "Generating HDL code from Simulink models has been a top item on their wish list. Now, engineers can design, verify, and implement hardware using Simulink models - the same models that can also generate embedded software."

Simulink HDL Coder generates bit-true, cycle-accurate Verilog and VHDL code from 80 standard blocks in Simulink and Signal Processing Blockset , as well as Mealy and Moore finite-state machines in Stateflow.  This generated code works with established hardware implementation and verification tools. Legacy HDL code and third-party HDL intellectual property can also be verified with Simulink models and integrated with the code that is automatically generated by Simulink HDL Coder.

Simulink HDL Coder also generates Verilog and VHDL test benches that enable reusing system simulation data for verification of the implemented design. "Manually writing test benches is a time-consuming, error-prone process," Karnofsky said, noting that design teams typically need to write 10 lines of HDL verification code for every line of hardware code. "Automatically generating test benches can help address the industry's verification bottleneck."

Engineers from more than 60 companies worldwide involved in the year-long prerelease test of Simulink HDL Coder praised the product's effectiveness in significantly improving their development process and hardware design quality. "By using Simulink HDL Coder, our team has been able to rapidly experiment with multiple design architectures and automatically generate HDL code," said Robert Peruzzi, senior member of technical staff, Agere Systems. "Simulink HDL Coder is an important addition to our Model-Based Design strategy. With Simulink HDL Coder, we can achieve the most efficient implementation of digital blocks on our mixed-signal integrated circuits and significantly reduce time spent on HDL implementation and verification."