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Bistable

Implement prioritized S-R flip-flop (bistable multivibrator)

Library

Control and Measurements/Logic

Description

The Bistable block implements the following logic:

  • When S input is true and R input is false, the flip-flop goes to the Set state. This is the first stable state, where Q is true.

  • When R is true and S is false, the flip-flop goes to the reset state. This is the second stable state, where Q is false.

  • When both S and R are true, the flip-flop goes to the prioritized state defined by the Select priority parameter.

  • When both S and R are false, the flip-flop stays in its previous state.

Dialog Box and Parameters

Select priority

Specify the prioritized state of Q.

Initial condition (state of Q)

Specify the initial value of the output Q.

Sample time (-1 for inherited)

Specify the sample time of the block, in seconds. Set to 0 to implement a continuous block.

Inputs and Outputs

S, [S]

The Set input. Must be Boolean. When the Select priority parameter value is Set, the input is named [S].

R, [R]

The Reset input. Must be Boolean. When the Select priority parameter value is Reset, the input is named [R].

Q

Bistable output. The signal is Boolean.

!Q

Bistable complement output. The signal is Boolean.

Characteristics

Direct FeedthroughYes
Sample TimeSpecified in the Sample Time parameter
Scalar ExpansionYes, of parameters
DimensionalizedYes
Zero-Crossing DetectionNo

Example

The power_Logicpower_Logic example shows the operation of the Bistable block.

The model sample time is parameterized with the variable Ts (default value Ts = 50e-3). To simulate a continuous Bistable block, specify Ts = 0 in the MATLAB® Command Window.

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