Determine frequency and fundamental component of signal phase angle
The PLL block models a Phase Lock Loop (PLL) closed-loop control system, which tracks the frequency and phase of a sinusoidal signal by using an internal frequency oscillator. The control system adjusts the internal oscillator frequency to keep the phases difference to 0.
The figure shows the internal diagram of the PLL.
The input signal is mixed with an internal oscillator signal. The DC component of the mixed signal (proportional to the phase difference between these two signals) is extracted with a variable frequency mean value. A Proportional-Integral-Derivative (PID) controller with an optional automatic gain control (AGC) keeps the phase difference to 0 by acting on a controlled oscillator. The PID output, corresponding to the angular velocity, is filtered and converted to the frequency, in hertz, which is used by the mean value.
Specify the minimum expected frequency of the input signal. This parameter sets the buffer size of the Mean (Variable Frequency) block used inside the block to compute the mean value.
Specify the initial phase and frequency of the input signal.
Specify the proportional, integral, and derivative gains of the internal PID controller. Use the gains to tune the PLL response time, overshoot, and steady-state error performances.
Specify the time constant for the first-order filter of the PID derivative block.
Specify the maximum positive and negative slope of the signal frequency.
Specify the second-order lowpass filter cut-off frequency.
Specify the sample time of the block, in seconds. Set to 0 to implement a continuous block.
When this check box is selected, the PLL block optimizes its performances by scaling the PID regulator signal according to the input signal magnitude. Select this option when the input signal is not normalized.
|Sample Time||Specified in the Sample Time parameter.|
Continuous when Sample Time = 0.
The PLL block is fed by a sinusoidal signal of 60 Hz, increasing to 61 Hz from 0.5 s to 1.5 s. Notice that the frequency reaches the new frequency in a short response time.
The PLL (3ph) block is fed by three-phase sinusoidal signals increasing from 60 Hz to 61 Hz between 0.5 and 1.5 seconds. The PLL (3ph) frequency reaches the new frequency faster than the PLL due to the additional phase information.
The model sample time is parameterized with the variable Ts (with a default value of 0). To discretize the PLL block, specify Ts=50e-6 in the MATLAB Command Window.