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EDA Simulator Link 3.1
Cosimulate and verify VHDL and Verilog using HDL simulators
EDA Simulator Link™ is a cosimulation interface that provides a bidirectional link between MATLAB® and Simulink® and HDL simulators from Mentor Graphics, Cadence, and Synopsys, enabling verification of VHDL®, Verilog®, and mixed-language implementations.
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Simulink and Model-Based Design enabled us to visualize the operation of the system as it was running, and the model served as a golden reference for the hardware.