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R2014a (Version 3.4)

Released: 6 Mar 2014

Version 3.4, part of Release 2014a, includes the following enhancements:

  • Code generation for enumeration data types
  • ZC706 target for IP core generation and integration into Xilinx EDK project
  • Automatic iterative clock frequency optimization
  • Code generation for FFT HDL Optimized and IFFT HDL Optimized blocks
  • HDL block library in Simulink

See the Release Notes for details.

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Previous Releases

R2013b (Version 3.3) - 5 Sep 2013

Version 3.3, part of Release 2013b, includes the following enhancements:

  • Model reference support and incremental code generation
  • Code generation for user-defined System objects
  • RAM inference in conditional MATLAB code
  • Code generation for subsystems containing Altera DSP Builder blocks
  • IP core integration into Xilinx EDK project for ZC702 and ZedBoard

See the Release Notes for details.

R2013a (Version 3.2) - 7 Mar 2013

Version 3.2, part of Release 2013a, includes the following enhancements:

  • Static range analysis for floating-point to fixed-point conversion
  • User-specified pipeline insertion for MATLAB variables
  • Resource sharing and streaming without over clocking
  • Generation of custom IP core with AXI4 interface

See the Release Notes for details.

R2012b (Version 3.1) - 11 Sep 2012

See highlights and screen shots.

Version 3.1, part of Release 2012b, includes the following enhancements:

  • Input parameter constants and structures in floating-point to fixed-point conversion
  • RAM, biquad filter, and demodulator System objects
  • Generation of MATLAB Function block in the MATLAB to HDL workflow
  • HDL code generation for Reed Solomon encoder and decoder, CRC detector, and multichannel Discrete FIR filter
  • Targeting of custom FPGA boards
  • Optimizations for MATLAB Function blocks and black boxes

See the Release Notes for details.

R2012a (Version 3.0) - 1 Mar 2012

See highlights and screen shots.

Version 3.0, part of Release 2012a, includes the following enhancements:

  • Automated fixed-point HDL Code generation from MATLAB code and System objects
  • Code generation from subsystems containing Xilinx® System Generator blocks
  • Turnkey workflow for Altera® boards
  • Instantiation of Xilinx and Altera floating-point IP
  • Code generation from any level of hierarchy with user-controllable flattening
  • Code generation for programmable coefficient and multiclock filters
  • Code generation for HDL CRC Generator, Bus Creator, and Bus Selector Blocks

See the Release Notes for details.