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HDL Verifier

FPGA-in-the-Loop Verification

HDL Verifier automates the implementation of HDL code on FPGA boards to enable FPGA-in-the-loop (FIL) verification, which complements HDL cosimulation by enabling you to run test scenarios faster. As a result you can explore more test cases and perform extensive regression testing on your designs. This approach also ensures that the algorithm will behave as expected in the real world.

HDL Verifier supports FIL verification over the Gigabit Ethernet interface for Xilinx and Altera FPGA boards. See a list of supprted hardware in the documentation.

Using FPGA-in-the-loop (FIL) verification to verify an HDL design.
Using FPGA-in-the-loop (FIL) verification to verify an HDL design. HDL Verifier supports Xilinx and Altera FPGA boards with Gigabit Ethernet for fast FPGA-based verification.

Using Custom Boards for FPGA-in-the-Loop Verification 2:17
Perform FPGA-based verification with custom boards using MATLAB® and Simulink® as test benches. Figures based on or adapted from figures and text owned by Xilinx, Inc. and used with permission. Copyright 2013 Xilinx, Inc.

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