This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™. The application uses Simulink® and an FPGA development board to verify the HDL implementation of a proportional-integral-derivative (PID) controller. In this example, Simulink generates the desired position of a motor and simulates the motor controlled by this PID controller.
Products required for this example:
MATLAB® and FPGA design software can either be locally installed on your computer or on a network accessible device. If you use software from the network you will need a second network adapter installed in your computer to provide a private network to the FPGA development board. Consult the hardware and networking guides for your computer to learn how to install the network adapter.
Use the following steps to set up your FPGA development board.
You must have a Gigabit Ethernet network adapter on your computer to run this example.
On Windows® 7, do the following steps:
On Windows® Vista, do the following steps:
On Windows XP®, do the following steps:
Use the ifconfig command to set up your local address. For example:
% ifconfig eth1 192.168.0.1
In this example, eth1 is the second Ethernet adapter on the Linux computer. Check your system to determine which Ethernet adapter is connected to the FPGA development board. The above command sets the local IP address to 192.168.0.1. If this address is in use by another computer on your network, change it to any available IP address on this subnet, such as 192.168.0.100.
Set up an examples folder, copy example files, set up access to FPGA design software, and open model.
1. Create a folder outside the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that the folder is located at C:\MyTests.
2. Start MATLAB and set the current directory in MATLAB to the folder you just created. For example,
3. Enter the following MATLAB command
This command copies all the source files under matlabroot\toolbox\shared\eda\fil\fildemos\fil_pid to your current directory. matlabroot is the MATLAB root directory on your system. You should have the following files in your working directory:
4. Set Up FPGA design software
Before using FPGA-in-the-Loop, make sure your system environment is set up properly for accessing FPGA design software. You can use the function hdlsetuptoolpath to add ISE or Quartus II to the system path for the current MATLAB session.
For Xilinx FPGA boards, run
hdlsetuptoolpath('ToolName', 'Xilinx ISE', 'ToolPath', 'C:\Xilinx\13.1\ISE_DS\IS E\bin\nt64\ise.exe');
This example assumes that the Xilinx ISE executable is C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64\ise.exe. Substitute with your actual executable if it is different.
For Altera boards, run
hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath','C:\altera\11.0\quart us\bin\quartus.exe');
This example assumes that the Altera Quartus II executable is C:\altera\11.0\quartus\bin\quartus.exe. Substitute with your actual executable if it is different.
5. Open the fil_pid.mdl model.
This model contains a fixed-point PID controller implemented with basic Simulink blocks. This model also contains a DC motor model controlled by this PID controller as well as the desired DC motor position as the input stimulus.
Run this model now and observe the desired and actual motor positions in the scope.
Launch the FPGA-in-the-Loop Wizard by doing the following:
From the Tools menu in the fil_pid model window, select Verification Wizards -> FPGA-in-the-Loop (FIL)....
Alternatively, you can enter the filWizard command at the MATLAB command prompt.
Set the hardware options for the FPGA development board.
1. For Board, select the FPGA development board connected to your host computer.
2. If you changed your computer's IP address to a different subnet from 192.168.0.x when you set up the network adapter, or if the default board IP address 192.168.0.2 is in use by another device, expand Advanced Options and change the Board IP address according to the following guidelines:
For example, if the host IP address is 192.168.8.2, then you can use 192.168.8.3 if it is available. Do not change Board MAC address.
3. Click Next to continue.
Specify the HDL design to be implemented in the FPGA.
1. Click Add and browse to the directory you created in Prepare Example Resources.
2. Select these HDL files:
These are the HDL design files to be verified on the FPGA board. 3. In the Source Files table, check the checkbox on the row of file Controller.vhd to specify that this HDL file contains the top-level HDL module.
The FIL Wizard automatically fills the Top-level module name field with the name of the selected HDL file; in this case, Controller. In this example, the top-level module name matches the file name so that you do not need to change it. If the top-level module name and file name did not match, you would manually correct the top-level module name in this dialog.
Click Next to continue.
The FIL Wizard parses the top-level HDL module Controller in Controller.vhd to obtain all the I/O ports and display them in the DUT I/O Ports table. The parser attempts to automatically determine the possible port types by looking at the port names and displays these signals under Port Type.
1. Review the port listing. If the parser assigned an incorrect port type for any given port, you can manually change the signal. For synchronous design, specify a Clock, Reset, or Clock enable signal. In this example, the FIL Wizard automatically fills the table correctly.
2. Click Next to continue.
1. Specify the folder for the output files. For this example, use the default option, which is a subfolder named Controller_fil under the current directory.
The Summary displays the locations of the ISE project file and the FPGA programming file. You may need those two files for advanced operations.
2. Click Build to start the build process.
During the build process, the following actions occur:
In the fil_pid model, replace the Controller subsystem with the FIL block generated in the new model. The modified fil_pid model now appears as shown in the following illustration:
1. Switch FPGA development board power ON.
2. Double-click the FIL block in the fil_pid model to open the block mask.
3. In the opened block mask, click Load.
If your board is connected to the host computer through the JTAG cable properly, a message window displays to indicate that the FPGA programming file is loaded successfully. Click OK to dismiss this dialog.
4. You can test if the FPGA board is connected to your host computer properly through the ping test. Launch a command-line window and enter the following command:
C:\MyTests> ping 192.168.0.2
If you changed the board IP address when you set up the network adapter, replace 192.168.0.2 with your board IP address. If the Gigabit Ethernet connection has been set up properly, you should see the ping reply from the FPGA development board.
1. In the FIL block mask, click the Signal Attributes tab.
2. Change the Data Type of the HDL signal control_signal to fixdt(1, 32, 28). This makes the FIL block set the output signal of the FPGA design-under-test (DUT) to the correct data type.
3. Click OK to close the block mask.
1. Start simulation of the fil_pid model.
2. When the simulation is done, view the waveform of the desired and actual positions of the motor in the scope. Note that the results of FIL simulation should match those of the Simulink reference model that you simulated in Prepare Example Resources.