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HDL Verifier

New Features

R2014a (Version 4.4)

Released: 6 Mar 2014

Version 4.4, part of Release 2014a, includes the following enhancements:

  • FPGA-in-the-Loop over JTAG for Altera FPGAs
  • Parameter Tuning for Generated TLM Component
  • Multiple Socket Control for Generated TLM Component
  • FPGA-in-the-Loop support for Altera Cyclone V SoC FPGA boards

See the Release Notes for details.

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Previous Releases

R2013b (Version 4.3) - 5 Sep 2013

Version 4.3, part of Release 2013b, includes the following enhancements:

  • SystemVerilog DPI component generation from Simulink
  • BEEcube miniBEE FPGA-in-the-Loop (FIL) support package
  • Additional FPGA board support for FIL, including Xilinx KC705 and Altera DSP Development Kit, Stratix V edition
  • Floating-point data type for cosimulation and FIL blocks
  • HDL file compilation ordering in Cosimulation Wizard

See the Release Notes for details.

R2013a (Version 4.2) - 7 Mar 2013

Version 4.2, part of Release 2013a, includes the following enhancements:

  • FPGA-in-the-loop testbench generation through HDL Workflow Advisor for MATLAB
  • HDL cosimulation testbench generation through HDL Workflow Advisor for MATLAB
  • Transaction Level Model generation using Simulink Coder

See the Release Notes for details.

R2012b (Version 4.1) - 11 Sep 2012

See highlights and screen shots.

Version 4.1, part of Release 2012b, includes the following enhancements:

  • Custom board APIs for FPGA-in-the-loop
  • System object for FPGA-in-the-Loop
  • 100 Base-T Ethernet support for FPGA-in-the-loop block
  • Automatic verification with cosimulation using HDL Coder

See the Release Notes for details.

R2012a (Version 4.0) - 1 Mar 2012

Version 4.0, part of Release 2012a, includes the following enhancements:

  • FPGA-in-the-Loop for Altera boards
  • System object for HDL cosimulation with MATLAB
  • Automated generation of cosimulation System object from existing HDL code
  • Use of FPGA board as Source block with FPGA-in-the-Loop
  • HDL cosimulation compatibility with Simulink Design Verifier

See the Release Notes for details.