Simulink HDL Coder 2.0

Simulink HDL Coder™ generates bit-true and cycle-accurate, synthesizable Verilog^® and VHDL^® code from Simulink^® models, MATLAB^® code, and Stateflow^® charts. The generated HDL code can be simulated and synthesized using industry-standard tools and then implemented on FPGAs and ASICs.

With Simulink HDL Coder you can control HDL architecture and implementation, highlight critical paths in the model, and generate hardware resource utilization estimates. For rapid verification, Simulink HDL Coder generates test benches and EDA Simulator Link™ cosimulation models, and provides code traceability to support the DO-254 workflow.