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transpose, .'

Transpose vector or matrix

Description

example

B = A.' returns the nonconjugate transpose of A, that is, interchanges the row and column index for each element. If A contains complex elements, then A.' does not affect the sign of the imaginary parts. For example, if A(3,2) is 1+2i and B = A.', then the element B(2,3) is also 1+2i.

B = transpose(A) is an alternate way to execute A.' and enables operator overloading for classes.

Examples

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Create a matrix of real numbers and compute its transpose. B has the same elements as A, but the rows of B are the columns of A and the columns of B are the rows of A.

A = magic(4)
A = 4×4

    16     2     3    13
     5    11    10     8
     9     7     6    12
     4    14    15     1

B = A.'
B = 4×4

    16     5     9     4
     2    11     7    14
     3    10     6    15
    13     8    12     1

Create a matrix containing complex elements and compute its nonconjugate transpose. B contains the same elements as A, except the rows and columns are interchanged. The signs of the imaginary parts are unchanged.

A = [1 3 4-1i 2+2i; 0+1i 1-1i 5 6-1i]
A = 2×4 complex

   1.0000 + 0.0000i   3.0000 + 0.0000i   4.0000 - 1.0000i   2.0000 + 2.0000i
   0.0000 + 1.0000i   1.0000 - 1.0000i   5.0000 + 0.0000i   6.0000 - 1.0000i

B = A.'
B = 4×2 complex

   1.0000 + 0.0000i   0.0000 + 1.0000i
   3.0000 + 0.0000i   1.0000 - 1.0000i
   4.0000 - 1.0000i   5.0000 + 0.0000i
   2.0000 + 2.0000i   6.0000 - 1.0000i

Input Arguments

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Input array, specified as a vector or matrix.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | logical | char | string | struct | cell | categorical | datetime | duration | calendarDuration
Complex Number Support: Yes

Tips

  • The complex conjugate transpose operator, A', also negates the sign of the imaginary part of the complex elements in A.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

GPU Code Generation
Generate CUDA® code for NVIDIA® GPUs using GPU Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

Introduced before R2006a